With the increased complexity of networking devices and protocols, it is increasing challenging to discover the source of a networking problem, especially when the problem occurs on a system on an application-specific integrated circuit (ASIC), such as an SoC. During SoC bring-up and board/system debugging, it is desirable to observe internal states of the SoC in an effort to determine a root cause of any issues. Design-for-debug (DFD) architectures are used during SoC bring-up and testing. For example, DFD may be used to observe internal nodes of the SoC for during functional debugging scenarios.
Due to increasing SoC complexity and decreasing time-to-market for SoC products, there exists a need for robust DFD architectures which support adequate testing of internal nodes in a time-efficient manner.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.